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<title>CMSIS-Core (Cortex-M): Intrinsic Functions for CPU Instructions</title>
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<div class="header">
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<a href="#func-members">Functions</a>  </div>
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<div class="title">Intrinsic Functions for CPU Instructions</div>  </div>
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<p>Functions that generate specific Cortex-M CPU Instructions.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a> (void)</td></tr>
<tr class="memdesc:gac71fad9f0a91980fecafcb450ee0a63e"><td class="mdescLeft">&#160;</td><td class="mdescRight">No Operation.  <a href="#gac71fad9f0a91980fecafcb450ee0a63e">More...</a><br/></td></tr>
<tr class="separator:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a> (void)</td></tr>
<tr class="memdesc:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Interrupt.  <a href="#gaed91dfbf3d7d7b7fba8d912fcbeaad88">More...</a><br/></td></tr>
<tr class="separator:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3efec76c3bfa2b8528ded530386c563"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (void)</td></tr>
<tr class="memdesc:gad3efec76c3bfa2b8528ded530386c563"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait For Event.  <a href="#gad3efec76c3bfa2b8528ded530386c563">More...</a><br/></td></tr>
<tr class="separator:gad3efec76c3bfa2b8528ded530386c563"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> (void)</td></tr>
<tr class="memdesc:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Event.  <a href="#ga3c34da7eb16496ae2668a5b95fa441e7">More...</a><br/></td></tr>
<tr class="separator:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92f5621626711931da71eaa8bf301af7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> (uint8_t value)</td></tr>
<tr class="memdesc:ga92f5621626711931da71eaa8bf301af7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set Breakpoint.  <a href="#ga92f5621626711931da71eaa8bf301af7">More...</a><br/></td></tr>
<tr class="separator:ga92f5621626711931da71eaa8bf301af7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93c09b4709394d81977300d5f84950e5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a> (void)</td></tr>
<tr class="memdesc:ga93c09b4709394d81977300d5f84950e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Synchronization Barrier.  <a href="#ga93c09b4709394d81977300d5f84950e5">More...</a><br/></td></tr>
<tr class="separator:ga93c09b4709394d81977300d5f84950e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a> (void)</td></tr>
<tr class="memdesc:gacb2a8ca6eae1ba4b31161578b720c199"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Synchronization Barrier.  <a href="#gacb2a8ca6eae1ba4b31161578b720c199">More...</a><br/></td></tr>
<tr class="separator:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a> (void)</td></tr>
<tr class="memdesc:gab1c9b393641dc2d397b3408fdbe72b96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Memory Barrier.  <a href="#gab1c9b393641dc2d397b3408fdbe72b96">More...</a><br/></td></tr>
<tr class="separator:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (32 bit)  <a href="#ga4717abc17af5ba29b1e4c055e0a0d9b8">More...</a><br/></td></tr>
<tr class="separator:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a> (uint32_t value)</td></tr>
<tr class="memdesc:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#gaeef6f853b6df3a365c838ee5b49a7a26">More...</a><br/></td></tr>
<tr class="separator:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="memItemLeft" align="right" valign="top">int16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga211618c03a0bf3264a7b22ad626d4f0a">__REVSH</a> (int16_t value)</td></tr>
<tr class="memdesc:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse byte order (16 bit)  <a href="#ga211618c03a0bf3264a7b22ad626d4f0a">More...</a><br/></td></tr>
<tr class="separator:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6f9f297f6b91a995ee199fbc796b863"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr>
<tr class="memdesc:gad6f9f297f6b91a995ee199fbc796b863"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reverse bit order of value.  <a href="#gad6f9f297f6b91a995ee199fbc796b863">More...</a><br/></td></tr>
<tr class="separator:gad6f9f297f6b91a995ee199fbc796b863"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a> (uint32_t value, uint32_t shift)</td></tr>
<tr class="memdesc:gaf66beb577bb9d90424c3d1d7f684c024"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate a value right by a number of bits.  <a href="#gaf66beb577bb9d90424c3d1d7f684c024">More...</a><br/></td></tr>
<tr class="separator:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a> (volatile uint8_t *addr)</td></tr>
<tr class="memdesc:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga9e3ac13d8dcf4331176b624cf6234a7e">More...</a><br/></td></tr>
<tr class="separator:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a> (volatile uint16_t *addr)</td></tr>
<tr class="memdesc:ga9feffc093d6f68b120d592a7a0d45a15"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga9feffc093d6f68b120d592a7a0d45a15">More...</a><br/></td></tr>
<tr class="separator:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a> (volatile uint32_t *addr)</td></tr>
<tr class="memdesc:gabd78840a0f2464905b7cec791ebc6a4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gabd78840a0f2464905b7cec791ebc6a4c">More...</a><br/></td></tr>
<tr class="separator:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a> (uint8_t value, volatile uint8_t *addr)</td></tr>
<tr class="memdesc:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#gaab6482d1f59f59e2b6b7efc1af391c99">More...</a><br/></td></tr>
<tr class="separator:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a> (uint16_t value, volatile uint16_t *addr)</td></tr>
<tr class="memdesc:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga0a354bdf71caa52f081a4a54e84c8d2a">More...</a><br/></td></tr>
<tr class="separator:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> (uint32_t value, volatile uint32_t *addr)</td></tr>
<tr class="memdesc:ga335deaaa7991490e1450cb7d1e4c5197"><td class="mdescLeft">&#160;</td><td class="mdescRight">STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga335deaaa7991490e1450cb7d1e4c5197">More...</a><br/></td></tr>
<tr class="separator:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> (void)</td></tr>
<tr class="memdesc:ga354c5ac8870cc3dfb823367af9c4b412"><td class="mdescLeft">&#160;</td><td class="mdescRight">Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga354c5ac8870cc3dfb823367af9c4b412">More...</a><br/></td></tr>
<tr class="separator:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga8cfeb5ffe0e49ec6b29dafdde92e5118">__SSAT</a> (int32_t value, uint32_t sat)</td></tr>
<tr class="memdesc:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga8cfeb5ffe0e49ec6b29dafdde92e5118">More...</a><br/></td></tr>
<tr class="separator:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76bbe4374a5912362866cdc1ded4064a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga76bbe4374a5912362866cdc1ded4064a">__USAT</a> (uint32_t value, uint32_t sat)</td></tr>
<tr class="memdesc:ga76bbe4374a5912362866cdc1ded4064a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000].  <a href="#ga76bbe4374a5912362866cdc1ded4064a">More...</a><br/></td></tr>
<tr class="separator:ga76bbe4374a5912362866cdc1ded4064a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90884c591ac5d73d6069334eba9d6c02"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr>
<tr class="memdesc:ga90884c591ac5d73d6069334eba9d6c02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Count leading zeros.  <a href="#ga90884c591ac5d73d6069334eba9d6c02">More...</a><br/></td></tr>
<tr class="separator:ga90884c591ac5d73d6069334eba9d6c02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac09134f1bf9c49db07282001afcc9380"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> (uint32_t value)</td></tr>
<tr class="memdesc:gac09134f1bf9c49db07282001afcc9380"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate Right with Extend (32 bit)  <a href="#gac09134f1bf9c49db07282001afcc9380">More...</a><br/></td></tr>
<tr class="separator:gac09134f1bf9c49db07282001afcc9380"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9464d75db32846aa8295c3c3adfacb41"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a> (uint8_t ptr)</td></tr>
<tr class="memdesc:ga9464d75db32846aa8295c3c3adfacb41"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDRT Unprivileged (8 bit)  <a href="#ga9464d75db32846aa8295c3c3adfacb41">More...</a><br/></td></tr>
<tr class="separator:ga9464d75db32846aa8295c3c3adfacb41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a> (uint16_t ptr)</td></tr>
<tr class="memdesc:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDRT Unprivileged (16 bit)  <a href="#gaa762b8bc5634ce38cb14d62a6b2aee32">More...</a><br/></td></tr>
<tr class="separator:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a> (uint32_t ptr)</td></tr>
<tr class="memdesc:ga616504f5da979ba8a073d428d6e8d5c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDRT Unprivileged (32 bit)  <a href="#ga616504f5da979ba8a073d428d6e8d5c7">More...</a><br/></td></tr>
<tr class="separator:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a> (uint8_t value, uint8_t ptr)</td></tr>
<tr class="memdesc:gad41aa59c92c0a165b7f98428d3320cd5"><td class="mdescLeft">&#160;</td><td class="mdescRight">STRT Unprivileged (8 bit)  <a href="#gad41aa59c92c0a165b7f98428d3320cd5">More...</a><br/></td></tr>
<tr class="separator:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a> (uint16_t value, uint16_t ptr)</td></tr>
<tr class="memdesc:ga2b5d93b8e461755b1072a03df3f1722e"><td class="mdescLeft">&#160;</td><td class="mdescRight">STRT Unprivileged (16 bit)  <a href="#ga2b5d93b8e461755b1072a03df3f1722e">More...</a><br/></td></tr>
<tr class="separator:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> (uint32_t value, uint32_t ptr)</td></tr>
<tr class="memdesc:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="mdescLeft">&#160;</td><td class="mdescRight">STRT Unprivileged (32 bit)  <a href="#ga625bc4ac0b1d50de9bcd13d9f050030e">More...</a><br/></td></tr>
<tr class="separator:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga263b9b2d9c06d731022873acddb6aa3f">__LDAB</a> (volatile uint8_t *ptr)</td></tr>
<tr class="memdesc:ga263b9b2d9c06d731022873acddb6aa3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire (8 bit)  <a href="#ga263b9b2d9c06d731022873acddb6aa3f">More...</a><br/></td></tr>
<tr class="separator:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5810ac0b87a37e321c2f909cd3860499"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5810ac0b87a37e321c2f909cd3860499">__LDAH</a> (volatile uint16_t *ptr)</td></tr>
<tr class="memdesc:ga5810ac0b87a37e321c2f909cd3860499"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire (16 bit)  <a href="#ga5810ac0b87a37e321c2f909cd3860499">More...</a><br/></td></tr>
<tr class="separator:ga5810ac0b87a37e321c2f909cd3860499"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga22a24f416b65c2f5a82d9f1162d9394d">__LDA</a> (volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire (32 bit)  <a href="#ga22a24f416b65c2f5a82d9f1162d9394d">More...</a><br/></td></tr>
<tr class="separator:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gace025d3a1f85d2ab9bae7288838d6bc8">__STLB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr>
<tr class="memdesc:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release (8 bit)  <a href="#gace025d3a1f85d2ab9bae7288838d6bc8">More...</a><br/></td></tr>
<tr class="separator:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga25691650de536f9b248b15f6dc4a3e70"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga25691650de536f9b248b15f6dc4a3e70">__STLH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr>
<tr class="memdesc:ga25691650de536f9b248b15f6dc4a3e70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release (16 bit)  <a href="#ga25691650de536f9b248b15f6dc4a3e70">More...</a><br/></td></tr>
<tr class="separator:ga25691650de536f9b248b15f6dc4a3e70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5429d7083fb8d30c43cecd3a861e1672">__STL</a> (uint32_t value, volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:ga5429d7083fb8d30c43cecd3a861e1672"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release (32 bit)  <a href="#ga5429d7083fb8d30c43cecd3a861e1672">More...</a><br/></td></tr>
<tr class="separator:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga513beada40cdd7123281f22482603bcc"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga513beada40cdd7123281f22482603bcc">__LDAEXB</a> (volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:ga513beada40cdd7123281f22482603bcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire Exclusive (8 bit)  <a href="#ga513beada40cdd7123281f22482603bcc">More...</a><br/></td></tr>
<tr class="separator:ga513beada40cdd7123281f22482603bcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga426b61640fc68f21b21ae4dc2726f3b4">__LDAEXH</a> (volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire Exclusive (16 bit)  <a href="#ga426b61640fc68f21b21ae4dc2726f3b4">More...</a><br/></td></tr>
<tr class="separator:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c74d923529f664eda099d1b2668b3c1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c74d923529f664eda099d1b2668b3c1">__LDAEX</a> (volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:ga3c74d923529f664eda099d1b2668b3c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load-Acquire Exclusive (32 bit)  <a href="#ga3c74d923529f664eda099d1b2668b3c1">More...</a><br/></td></tr>
<tr class="separator:ga3c74d923529f664eda099d1b2668b3c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga590724a32a229978536fbbbd6cc82536"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga590724a32a229978536fbbbd6cc82536">__STLEXB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr>
<tr class="memdesc:ga590724a32a229978536fbbbd6cc82536"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release Exclusive (8 bit)  <a href="#ga590724a32a229978536fbbbd6cc82536">More...</a><br/></td></tr>
<tr class="separator:ga590724a32a229978536fbbbd6cc82536"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga047c3bebca3d0ae348ab8370a046301d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga047c3bebca3d0ae348ab8370a046301d">__STLEXH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr>
<tr class="memdesc:ga047c3bebca3d0ae348ab8370a046301d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release Exclusive (16 bit)  <a href="#ga047c3bebca3d0ae348ab8370a046301d">More...</a><br/></td></tr>
<tr class="separator:ga047c3bebca3d0ae348ab8370a046301d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7f955b91595cfd82a03e4b437c59afe"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gae7f955b91595cfd82a03e4b437c59afe">__STLEX</a> (uint32_t value, volatile uint32_t *ptr)</td></tr>
<tr class="memdesc:gae7f955b91595cfd82a03e4b437c59afe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Store-Release Exclusive (32 bit)  <a href="#gae7f955b91595cfd82a03e4b437c59afe">More...</a><br/></td></tr>
<tr class="separator:gae7f955b91595cfd82a03e4b437c59afe"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the <a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> for detailed information about these Cortex-M instructions.</p>
<dl class="section note"><dt>Note</dt><dd>When using the <b>Arm Compiler Version 5 Toolchain</b> the following <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> are implemented using the Embedded Assembler. As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information) it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><em>define __NO_EMBEDDED_ASM</em></b>:<ul>
<li><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a></li>
<li><a class="el" href="group__intrinsic__CPU__gr.html#ga211618c03a0bf3264a7b22ad626d4f0a">__REVSH</a></li>
<li><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> </li>
</ul>
</dd></dl>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="ga92f5621626711931da71eaa8bf301af7"></a>
<div class="memitem">
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          <td class="memname">void __BKPT </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint. </td></tr>
  </table>
  </dd>
</dl>

</div>
</div>
<a class="anchor" id="ga354c5ac8870cc3dfb823367af9c4b412"></a>
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          <td class="memname">void __CLREX </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000]. </p>

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</div>
<a class="anchor" id="ga90884c591ac5d73d6069334eba9d6c02"></a>
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          <td class="memname">uint8_t __CLZ </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function counts the number of leading zeros of a data value.</p>
<p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __CLZ is implemented in software.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>

</div>
</div>
<a class="anchor" id="gab1c9b393641dc2d397b3408fdbe72b96"></a>
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          <td class="memname">void __DMB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>

</div>
</div>
<a class="anchor" id="gacb2a8ca6eae1ba4b31161578b720c199"></a>
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          <td class="memname">void __DSB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>

</div>
</div>
<a class="anchor" id="ga93c09b4709394d81977300d5f84950e5"></a>
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          <td class="memname">void __ISB </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>

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</div>
<a class="anchor" id="ga22a24f416b65c2f5a82d9f1162d9394d"></a>
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          <td class="memname">uint32_t __LDA </td>
          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a LDA instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

</div>
</div>
<a class="anchor" id="ga263b9b2d9c06d731022873acddb6aa3f"></a>
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          <td class="memname">uint8_t __LDAB </td>
          <td>(</td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a LDAB instruction for 8 bit value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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</div>
<a class="anchor" id="ga3c74d923529f664eda099d1b2668b3c1"></a>
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          <td class="memname">uint32_t __LDAEX </td>
          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a LDA exclusive instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>Executes a LDAB exclusive instruction for 8 bit value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">uint16_t __LDAEXH </td>
          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Executes a LDAH exclusive instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">uint16_t __LDAH </td>
          <td>(</td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a LDAH instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function executed an Unprivileged LDRT command for 8 bit value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>

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          <td class="memname">uint8_t __LDREXB </td>
          <td>(</td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*addr) </dd></dl>

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          <td>(</td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*addr) </dd></dl>

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          <td class="memname">uint32_t __LDREXW </td>
          <td>(</td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>addr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*addr) </dd></dl>

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          <td class="memname">uint16_t __LDRHT </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an Unprivileged LDRT command for 16 bit values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>

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          <td class="memname">uint32_t __LDRT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>ptr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executed an Unprivileged LDRT command for 32 bit values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>

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          <td class="memname">void __NOP </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function does nothing. This instruction can be used for code alignment purposes. </p>

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          <td class="memname">uint32_t __RBIT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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          <td class="memname">uint32_t __REV </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
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<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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          <td class="memname">uint32_t __REV16 </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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          <td class="memname">int16_t __REVSH </td>
          <td>(</td>
          <td class="paramtype">int16_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>

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          <td class="memname">uint32_t __ROR </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>shift</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function rotates a value right by a specified number of bits.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be shifted right </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">shift</td><td>Number of bits in the range [1..31] </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>

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          <td class="memname">uint32_t __RRX </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to rotate </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>

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          <td class="memname">void __SEV </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>

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          <td class="memname">int32_t __SSAT </td>
          <td>(</td>
          <td class="paramtype">int32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>sat</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function saturates a signed value [not for Cortex-M0, Cortex-M0+, or SC000]. The Q bit is set if saturation occurs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [1..32] </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>

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          <td class="memname">void __STL </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a STL instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">void __STLB </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Executes a STLB instruction for 8 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">uint32_t __STLEX </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Executes a STL exclusive instruction for 32 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">uint32_t __STLEXB </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Executes a STLB exclusive instruction for 8 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">uint32_t __STLEXH </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Executes a STLH exclusive instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">void __STLH </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Executes a STLH instruction for 16 bit values. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>

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          <td class="memname">void __STRBT </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function executed an Unprivileged STRT command for 8 bit values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">uint32_t __STREXB </td>
          <td>(</td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint8_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

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          <td class="memname">uint32_t __STREXH </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint16_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

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          <td class="memname">uint32_t __STREXW </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">volatile uint32_t *&#160;</td>
          <td class="paramname"><em>addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
<dd>
1 Function failed </dd></dl>

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          <td class="memname">void __STRHT </td>
          <td>(</td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an Unprivileged STRT command for 16 bit values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">void __STRT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>ptr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function executed an Unprivileged STRT command for 32 bit values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">uint32_t __USAT </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>sat</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>This function saturates an unsigned value [not for Cortex-M0, Cortex-M0+, or SC000]. The Q bit is set if saturation occurs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [0..31] </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>

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          <td class="memname">void __WFE </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p>
<ul>
<li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul>
<li>An exception, unless masked by the exception mask registers or the current priority level.</li>
<li>An exception enters the Pending state, if SEVONPEND in the System Control Register is set.</li>
<li>A Debug Entry request, if Debug is enabled.</li>
<li>An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.</li>
</ul>
</li>
</ul>
<ul>
<li>If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately. </li>
</ul>

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          <td class="memname">void __WFI </td>
          <td>(</td>
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          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p>
<ul>
<li>A non-masked interrupt occurs and is taken.</li>
<li>An interrupt masked by PRIMASK becomes pending.</li>
<li>A Debug Entry request. </li>
</ul>

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